An analog-to-digital converter (ADC) is a device that converts a continuous physical quantity (e.g., a voltage) to a digital number that represents the quantity's amplitude. The conversion involves quantization (or sampling) of the input, which the ADC performs periodically. The result is a sequence of digital values that have been converted from a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.
High-speed high-performance ADCs use switched-capacitor based input sampling network. Large capacitors switched on and off at high sample speed make it difficult for the external circuits to drive the ADCs. In order to minimize such difficulties, high-performance on-chip analog input buffers are inserted in front of the ADCs. The on-chip analog input buffer needs to maintain high linearity (85 dB) at very high frequencies (in the order of 500 MHz), while driving a large capacitor (in the order of 3 pF) being switched at very high sampling speed (500 Msps).
Because there is no industry standardization regarding ADC input structures, however, each ADC must be examined on its own before an input interface circuitry is designed. In many implementations, the analog input to an ADC is connected directly to a sample-and-hold capacitor, which generates transient currents that must be buffered from the signal source. And in those cases, an analog buffer may be provided.
Turning to FIG. 1, an example of a conventional analog input buffer is provided. Particularly, buffer 100 includes emitter-follower transistor Q1 configured to receive input signal vin at its base terminal and thereby allowing current IQ1 to develop. The node between transistors Q1 and Q2 provide output vo across capacitor CL, which models the sample-and-hold capacitor within an ADC. Current IQ1 is divided between IQ2 (through Q2) and ICL (through CL). Transistors Q3 and Q2 are in a current mirror configuration as shown, where the collector terminal of Q3 is coupled to current source Ibias.
In buffer 100, current ICL is a dynamically changing, time-varying current; which means that current IQ1 effectively contains an AC component (because IQ1=IQ2+ICL). When the input signal amplitude is large and the input frequency is high, the current flowing in the large sample capacitor of the ADC is a large AC current. This AC current combines with the DC bias current and flows through the emitter-follower device. This results in non-linear operation of the emitter follower and the signal being fed to the ADC becomes distorted. Therefore, to ensure linear operation of the circuit, IQ2 must usually be provided as a DC bias current (that is, a mirror of Ibias) that is much larger than ICL.
FIG. 2 provides an example of a prior art input buffer design that can provide higher linearity with a smaller Ibias. Buffer 200 is similar to buffer 100, but with the addition of cascode transistor Q4 and capacitor C1 as shown. Cascode transistor Q4 is biased with vB, and C1 is coupled between vin and the emitter terminals of transistor Q4. The AC voltage across C1 is similar to the AC voltage across CL, therefore IC1=ICL for the case where C1=CL. Moreover, in such a situation, IQ1 is equal to IQ2 and is proportional to the constant current Ibias.